Q: My understanding is that FPGAs have come down in price. How has that cost and price scenario worked out for Actel, and what are the key market drivers for Actel as a differentiated company?

A: A large percentage of revenues for the two big PLD companies come from the communication and data processing sectors, whereas at Actel we have a much smaller percentage of our revenues from those two markets. We have a much larger proportion of our revenues coming from the industrial, consumer and automotive markets. Gartner is forecasting that by 2010, the industrial segment will occupy a much larger proportion of the overall PLD market. Overall, Gartner expects the total FPGA/PLD market to grow to US$6.7 billion in 2010, as compared with US$2.3 billion in 2002.
     Gartner is forecasting growth in the industrial segment, the consumer segment, and also in the military and aerospace, and automotive segments in particular. Those four segments, according to Gartner, will come to occupy a much larger percentage of the overall PLD market, and those are precisely the segments where Actel is strong.
     In July of last year, we announced that communication accounts for 16% of our revenue, consumer 14%, industrial 33% and “aero and mil” (aerospace and military) 27%. At Xilinx, on the other hand, communication alone accounts for 45% of their market, in terms of revenue.
     The consumer segment, and portable devices in particular, we expect to do well. In the industrial segment, we are able to offer our Fusion mixed signal product, and in “mil aero” we are able to offer neutron immune products, as I explained. Gartner Dataquest also made the comment that communication and data processing seem to be growing less than was expected.
     So far we have focused on these key segments with our radiation-tolerant RTAX-S products for system-critical requirements, and with IGLOO and PA3 “value” solutions. PA3 offers low cost; IGLOO offers all the advantages of low power. The difference between the two is that if you need absolutely low costing in an FPGA, you will use PA3. If you need an absolutely low power FPGA, then you will use IGLOO. IGLOO, currently, is slightly more expensive than PA3.
     We also focus on a programmable system chip with our Fusion product, as well as with the ARM Cortex-M1. In fact, with Cortex-M1, we pay the royalty to ARM for our customers, so that our customers will find it easy to adopt.
     An important feature of IGLOO’s low power capability is what we call “Flash*Freeze,” where a device such as a PDA or smartphone can be powered down to an absolutely low power mode. With this feature, we are answering the requirements of a segment that is now very large, including portable entertainment, portable gaming, digital cameras, and in the industrial and medical sectors, portable medical devices and test equipment. The automotive segment also has a lot of new applications that could take advantage of IGLOO.
     The complete IGLOO range goes from 30,000 gates to 3 million gates. The 30,000-gate devices are very suitable for portable devices where what is required is a simple glue logic interface. The packages are all pin-to-pin compatible, so that customers can move up and down within that range, without having to do a new board layout.
     Fusion Programmable System Chips (PSCs), as you know, are targeted for mixed signal applications, and in particular industrial control and any system that may need to monitor current, or voltage or temperature. A single Fusion PSC could handle this type of application, as opposed to a set of discrete components. And incidentally, because Fusion is both mixed signal in its capability and flash-memory based it can also handle data logging, something you cannot really do with SRAM based technologies, where there is no A/D function or non-volatile memory.
     With the Cortex-M1, we work very closely with ARM to enable an embedded processor to target an FPGA fabric. ARM is very comfortable with this arrangement since we are able to secure IP, and ARM does not have to worry about its processor IP being pirated. If the FPGAs were SRAM based, the business model would be rather more challenging, whereas for us it’s easy. We can give the Cortex processor to customers for free and track the shipments. And because of the security mechanisms on our chip, including 128-bit AES encryption and the fact that they are flash based, it would be almost impossible for the design to be pirated. The security mechanisms can also include product ID numbers.

Q: FPGAs can also be used for ASIC design prototyping. What kind of cost and time to market advantages could we be looking at there?

A: FPGAs have traditionally been used for chip prototyping, but with the advance to sub-micron and deep sub-micron geometries, the ASIC vendors are becoming a lot more cost-conscious. More and more customers are starting to use FPGAs not simply for pre-production pilot runs but also for mass production That approach offers both lower cost and a time-to-market advantage.
     That trend has been accelerated by the fall in price of FPGAs. Nowadays, you can find FPGA devices that cost only one to two dollars, whereas in previous years there was a huge price gap between ASICs and FPGAs. With FPGAs that cost only one to three dollars, you can go to very high production volumes without having to go to ASIC production. The number of features and gates now available in FPGAs in that price band does not warrant the migration to an ASIC, which would then incur NREs (non-recurring engineering expenses) for the masks and so on.
     Of course, I am talking about very high volume opportunities. Obviously, you still have customers who produce relatively low volumes but at a high ASP, but in the Asia Pacific, I do see that there are now a lot more new consumer type applications, where previously the vendor purchased a one-to-three dollar ASIC and now they buy a one-to-three-dollar FPGA.
     Another factor, here, is that when chip geometries continue to shrink, what really determines the die size of an ASIC is the I/O ring. In that situation, the number of gates on a FPGA becomes less and less of a cost issue. At the same time, the FPGA is programmable, making it a lot more user-friendly, while the inventory concerns you would have with a single-application ASIC are also diminished.

Q: What would be the actual impact of using FPGAs, as opposed to an ASIC, on mask costs?

A: This question is quite complicated. One would need to determine the speed of the application and also how large a design one needs. If you need a very fast system design with a lot of gates, then you will need to consider the density of the FPGA, which can be quite complex. But if your application does not need very fast logic, instead of using a 90-nanometer geometry you could probably go to 0.13 micron or even 0.18 micron. So the value proposition really depends on the application the customer is engineering. Usually, for systems that require 90-nanometer geometry, the NREs are quite high, but it’s difficult to put an exact figure on that because different ASIC companies have their own way of amortizing the cost.

Q: In terms of low cost FPGAs, you say the PA3 line is your lowest cost product. What are its competitor products in today’s market?

A: Customers who are using Xilinx’ Spartan FPGAs or Altera’s Cyclone FPGAs quite can often consider our ProASIC3 (PA3). The PA3 is a good example of the advantages of a flash-based device, as opposed to SRAM based products. It’s live at power up; it’s low power; it’s non-volatile, and because it’s non-volatile it’s secure and radiation error immune. Finally, it has a low total system cost.